The present invention relates to sense amplifier circuits used to detect the states of non-volatile memory cells in a non-volatile memory array.
Electrically erasable and programmable read only memories (EEPROMs) and flash erasable and programmable read only memories (flash EPROMs) are two types of non-volatile memory (NVM) devices. NVM cells typically comprise a sort of modified field-effect transistor (FET) that includes an electrically isolated floating gate (e.g., polycrystalline silicon or oxide-nitride-oxide (ONO)) for controlling conduction between source and drain regions of the EEPROM cell. A gate dielectric (bottom oxide) is formed between the floating gate and an underlying channel region between the source and drain regions. A control gate is provided adjacent to (e.g., above) the floating gate, and is separated from the floating gate by an inter-gate dielectric (top oxide). The data value stored by an EEPROM cell is determined by the amount of charge stored in the floating gate, which is controlled during program and erase operations by applying predetermined voltages across the floating gate. For example, during a program (write) operation, a net negative charge is transferred to and stored by the floating gate using a technique such as hot electron injection or Fowler-Nordheim (FN) tunneling. In this programmed state, the negative charge stored by the floating gate resists current flow between the source and drain regions of the memory cell when the control gate is asserted (i.e., pulled high). Conversely, an erase v operation transfers a neutral charge to the floating gate using FN tunneling. In the erased state, the neutral charge stored by the floating gate permits current flow between the source and drain regions of the memory cell when the control gate is asserted. NVM devices have an advantage over other volatile memories (e.g., static random access memory (SRAM) devices or dynamic RAM (DRAM) devices) in that the floating gate charge is stored essentially indefinitely (i.e., until a subsequent program/erase operation). That is, the charge stored by the floating gate of an NVM cell is retained even if power to the NVM device is disconnected, whereas data stored in volatile memory devices is lost when power is disconnected.
FIG. 1 is a simplified block diagram showing a conventional non-volatile memory (NVM) device 100. NVM device 100 includes an array 110 of NVM cells 115, and peripheral control circuitry located around array 110 including an input/output (I/O) control circuit 120, a word line control circuit 130, an optional address decoder 135, a bit line control circuit 140, a bit line (Y) decoder 145, and a sense amplifier circuit 150. NVM cells 115 are arranged in rows and columns such that the control gates of each row of NVM cells 115 are connected to an associated word line WL0 through WL7, and each column of NVM cells 115 is connected to an associated pair of bit lines BL0 through BL8. As indicated on the upper portion of FIG. 1, NVM device 100 also includes a reference NVM cell array 170 including several reference NVM cells. The reference NVM cells of reference NVM cell array 170 are utilized as discussed below.
Operation of NVM device 100 will now be briefly described with reference to FIG. 1.
During program and erase operations, address data and an associated data word are respectively transmitted via I/O control circuit 120 to word line control circuit 130 (via optional address decoder 135) and to bit line control circuit 140. Word line control circuit 130 uses the address data to pass an appropriate program/erase voltage onto an associated word line (e.g., word line WL0), and bit line control circuit 140 then drives selected bit lines to transmit appropriate program/erase voltage needed to program selected NVM cells 115 of the selected row. According to one convention, the NVM cells 115 that are programmed store a logic xe2x80x9c1xe2x80x9d data value, and those NVM cells that remain erased (unprogrammed) store a logic xe2x80x9c0xe2x80x9d data value. During xe2x80x9cflashxe2x80x9d erase operations, the word lines and bit lines are maintained at an appropriate voltage level that causes all programmed NVM cells 115 to be erased. Those of ordinary skill in the art will recognize that the above explanation is greatly simplified, and that many variations in the described operations are possible.
NVM cells 115 are typically read (sensed) by comparing currents ICELL[0]-ICELL[7] passing through selected NVM cells (or voltages derived from the currents through the cells) to reference currents IREF[0]-IREF[7] (or voltages) derived from corresponding reference cells in reference NVM array 170. In particular, during read operations, address data associated with selected data word is transmitted via I/O control circuit 120 to word line driver circuit 130, which uses the address data to apply an appropriate read voltage on the associated word line (e.g., word line WL1), thereby causing the selected currents ICELL[0]-ICELL[7] to pass from an associated word of the NMV cells onto, for example, bit lines BL0 through BL7. The thus-read data word is then transmitted via Y-decoder 145 to sense amplifier circuit 150, which compares the currents ICELL[0]-IREF[7] with corresponding reference currents. IREP[0]-IREF[7]. When the sensed current (or voltage) read from a particular NVM cell 115 is larger than the corresponding reference current (or voltage) generated by the reference NVM cell, the NVM cell 115 is considered to be erased. Conversely, if the sensed current (or voltage) is smaller than the corresponding reference current (or voltage), the read NVM cell 115 is considered to be programmed. Sense amplifier circuit, 150 then outputs detected data values D[0]-D[7] based on these comparisons to I/O control circuit 120 for transmission out of NVM device 100.
FIG. 2 is a simplified circuit diagram showing a portion of conventional NVM circuit 100 that illustrates a conventional sensing scheme for determining the programmed/erased state of a selected NVM cell 115-1. In particular, FIG. 2 shows portions of NVM array 110, bit line control circuit 140, Y-decoder circuit 145, sense amplifier circuit 150, and reference array 170. The portion of NVM array 110 shown in FIG. 2 includes a selected NVM cell 115-1, which is connected between bit lines BL0 and BL1 and is controlled by a word line voltage transmitted on word line WL1. FIG. 2 also shows a portion of reference NVM array 170 including a reference NVM cell 115-R1, which is connected between reference bit lines BLR0 and BLR1 and is controlled by a word line voltage transmitted on a word line WLR1 (which may be the same word line WL1 used to access selected NVM cell 115-1).
Bit line control circuit 140 and Y-decoder circuit 145, which are typically implemented by multiplexing circuits, are represented by a pass transistors 240 and 245, respectively, which are controlled by control signals VCOLxe2x80x94SEL1 and VCOLxe2x80x94SEL, respectively.
Sense amplifier circuit 150 includes a comparator (e.g., operational amplifier) 250 having a first (inverting) input terminal connected to a node N1, and a second (non-inverting) input terminal connected to a reference node RN1. Node N1 is connected to the gate and drain terminals of a first PMOS transistor 252, whose source terminal is connected to system voltage VDD. Node N1 is also coupled to bit line BL1 via a first NMOS clamp transistor 254, whose conductance is controlled by a bias voltage VBIAS to prevent soft programming, and via pass transistor 245 of Y-decoder circuit 145. Reference node RN1 is connected to the gate and drain terminals of a second PMOS transistor 254, whose source terminal is also connected to system voltage VDD. Reference node RN1 is coupled to reference array 170 via a second NMOS clamp transistor 257, which is also controlled by bias voltage VBIAS. Note that PMOS transistors 252 and 257 have a relatively small transconductance, and NMOS transistor 254 and 259 have a relatively large transconductance.
Similar to NVM array 110, reference array 170 includes a reference cell 115-R1 connected between first reference bit line BLR0 and second reference bit line BLR1, and is controlled by a word line voltage transmitted on reference word line WLR1. Reference bit line BLR0 is selectively coupled to ground through a multiplexer 272, which is represented by a pass-transistor 273,using a reference control voltage VREFxe2x80x94COLxe2x80x94SEL1. Similarly, reference bit line BLR1 is selectively coupled to sense amplifier 150 through a multiplexer 275, which is represented by a pass transistor 277, using a reference control voltage VREFxe2x80x94COLxe2x80x94SEL.
According to the example depicted in FIG. 2, NVM cell 115-1 is read by comparing a cell current ICELL[1] passing through NVM cell 115-1 with a reference current IREF[1] passing through reference NVM cell 115-R1. Cell current ICELL[1] is generated by coupling bit line BL0 to ground via bit line control circuit 140 (e.g., by turning on pass transistor 240), and coupling bit line BL1 to sense amplifier circuit 150 via Y-decoder 145 (e.g., by turning on pass transistor 245). Similarly, reference current IREF[1] is generated by coupling reference bit line BLR0 to ground (e.g., by turning on pass transistor 273), and coupling reference bit line BLR1 to sense amplifier circuit 150 (e.g., by turning on pass transistor 275). Cell current ICELL[1] of selected NVM cell 115-1 is converted to a corresponding cell voltage on node N1, which in turn is applied to the first input terminal of comparator 250. Reference current IREF[1] of reference cell 115-R1 is converted into a corresponding second voltage on reference node RNl, which is applied to the second input terminal of comparator 250. When cell current ICELL[1] through NVM cell 115-1 (or the corresponding voltage at node N1) is larger than reference current IREF[1] through reference NVM cell 115-R1 (or the corresponding voltage at reference node RN1), NVM cell 115-1 is considered to be erased, and comparator 250 generates a high voltage data output signal D[1]. Conversely, if the sensed cell current ICELL[1] (or voltage) is smaller than the reference current IREF[1] (or voltage), then NVM cell 115-1 is considered to be programmed, and comparator 250 generates a low voltage data output signal D[1].
Recently it has become increasingly desirable to reduce the supply voltage VDD of NVM arrays from sub-3 Volts to sub-2 Volts for use in low power applications, such as hand held digital devices. However, reducing supply voltage VDD below 3 Volts using the conventional sensing scheme described above is not possible due to voltage drops caused by the various multiplexers. As mentioned above, clamp transistors 254 and 259 are required to avoid soft programming. The source voltage of clamp transistor 254 limits the bit line voltage on bit line BL1 to VBIAS minus the threshold voltage of clamp transistor 254. Therefore, the minimum supply voltage VDD required to read NVM cell 115-1 may be represented by:
VDD(min)=VBITLINE+VDSN(254)+VTP+xcex94VDSPxe2x80x83xe2x80x83(EQ. 1)
where VBITLINE is the voltage on bit line BL1, VDSN(254) is the voltage across clamp NMOS transistor 254, VTP is the threshold voltage of PMOS transistor 252, and xcex94VDSP is the xe2x80x9ceffectivexe2x80x9d voltage VGS-VTP of PMOS transistor 252. That is, xcex94VDSP equals             2      *              I        CELL            *              (                  Lp          /          Wp                )                    (                        μ                      0            ⁢            P                          *                  C                      0            ⁢            X                              )      
(under the most simple MOS transistor model for saturation operating region), and is linearly related to the square root of the cell current ICELL through PMOS transistor 252. For example, assuming VBITLINE is limited to 1 Volt, VDSN=0.2 Volts, VTP=1 Volt, and xcex94VDSP=0.3 Volts, then the minimum value for VDD is limited to above 2.5 Volts.
One approach utilized to facilitate the use of a sub-2 Volt supply voltage to drive an NVM device is to utilize charge pumps that generate sufficiently high bit line voltages from the sub-2 Volt supply to support the conventional sensing scheme described above. However, in addition to producing high bit line voltages, charge pumps generate significant noise (i.e., voltage xe2x80x9cripplexe2x80x9d) that can affect the accuracy of the sense amplifier. In addition, the inherent low power efficiency of the charge pump will cause excessive power consumption and reduced battery life.
What is needed is a sense amplifier and NVM cell sensing process that will both operate at very low system voltages (i.e., below 2.5 Volts) and minimize power consumption.
The present invention is directed to low voltage sensing circuits for NVM devices that utilizes voltage supply circuits or source-follower circuits to increase bit line currents/voltages using a low (i.e., sub-2 Volt) supply voltage without the need for a charge pump, thereby minimizing power consumption.
Similar to conventional sensing schemes that compare a bit line current (or voltage) generated by a selected NVM cell with a reference bit line current (or voltage) generated by a reference NVM cell, the sensing circuit of the present invention includes a comparator (e.g., an operational amplifier) and a pair of PMOS transistors that are respectively coupled to the bit line and the reference bit line. The comparators includes a first (e.g., inverting) input terminal connected to the gate terminal of a first PMOS transistor, which is coupled to the bit line, and a second (e.g., non-inverting) input terminal connected to the gate terminal of a second PMOS transistor, which is coupled to the reference bit line.
In accordance with a first embodiment of the present invention, a voltage supply is connected between the gate and drain terminals of each PMOS transistor such that the voltage at the drain terminal of each PMOS transistor is a predetermined voltage level above the voltage applied to the corresponding comparator input terminal. Accordingly, the voltages passed to the cell bit line and reference bit line are increased to facilitate proper NVM cell read operations, while the voltage applied to the comparator input terminals remains relatively low. By sensing currents through (or voltages across) the selected NVM cell and reference NVM cell in this manner, the minimum system voltage required to drive the NVM device is reduced to sub-2 Volts without requiring a charge pump. Further, the sensing circuit of the present invention facilitates operation of the PMOS transistors in their linear region, as opposed to saturated operation, thereby allowing an even further reduction in the required minimum system voltage.
In accordance with a second embodiment of the present invention, a source-follower circuit is connected between the gate and drain terminals of each PMOS transistor, thereby increasing the voltage at the drain terminal of each PMOS transistor by a predetermined voltage level in a manner similar to that of the first embodiment (discussed above). Each source-follower includes an NMOS transistor connected in series with a current source circuit between the system voltage and ground. The gate terminal of each NMOS transistor is connected to the drain terminal of its corresponding PMOS transistor, and a node located between the NMOS transistor and current source is connected to the corresponding input terminal of the comparator.